1. Field of the Invention
The present invention is related to a generic sequence controller of distributed functional units.
2. Background Art
Advances in integrated circuit technology have made it possible to embed an entire system, including a processor core, a memory unit, a high performance bus, and a programmable logic, in a single semiconductor device. Present techniques allow for the fabrication of up to approximately fifty million gates per chip. Higher gate densities and clock frequencies will allow the development of Systems-On-A-Chip (SoCs) in which processing circuitry, memory and input/output devices are all fabricated together on a chip and distributed in a single package. This type of programmable semiconductor device is commonly referred to as a system-on-chip (SoC), or a configurable system-on-chip (CSoC). For example, a microprocessor or microcontroller may be fabricated together with on-chip memory for storing the operating system and/or the basic input/output system (BIOS). The applications for SoCs are numerous, including portable personal computers, mobile personal communicators, and similar compact systems. The SoC provides many advantages over traditional processor-based designs. It is an attractive alternative to multi-chip designs because the integration of components into a single device increases overall speed while decreasing size. The SoC is also an attractive alternative to fully customized chips, such as an ASIC (application specific integrated circuit), because ASIC designs tend to have a significantly longer development time and larger development costs.
The invention proposes a simple method for controlling distributed functional units (FU) in an SoC system. It offloads the main system processor from intermediate status monitoring.
U.S. Pat. No. 6,963,340 to Alben discloses the microcontroller functions as a sequencer for controlling the timing of power up and/or power down operations by one or both of a graphics processor and a display device. For example, the microcontroller is implemented in a graphics processor and controls the timing which the graphics processor and a display device coupled thereto perform the steps required to enter or leave a “suspend” mode (or other reduced power consumption mode), or perform the sequence of steps comprising a full power up (or power down) operation. However, it does not offload the processor from intermediate status monitoring.
Further, the prior art does not address an SOC environment with distributed functional units each with their own execution/instruction cache. Prior art does not mention utilizing such a controller for increasing parallelism within the system.
Accordingly, it would be highly desirable to provide an improved sequencer for offloading main processor from controlling all other functional units. Once configured, it can function independent from said main processor. Further, the present invention is simple to configure and fully expandable to accommodate unlimited functional units. Runtime is reconfigurable by the main processor and the functional units. The present invention supports different levels of functional units.
Further objectives and advantages of the present invention will become apparent from a careful reading of a detailed description provided hereinbelow, with appropriate reference to accompanying drawings.